1. Technical Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, a wiring structure using a film with a low dielectric constant and a method of manufacturing the same.
2. Description of the Related Art
In accordance with the microminiaturization of semiconductor devices, multilayer interconnection becomes necessary. Also, in accordance with the lowering of the voltage and speedup of operation of semiconductor devices, a lowering of the dielectric constant of the interlayer insulation film becomes necessary. Particularly, in logic-system semiconductor devices, an increase in resistance and an increase in parasitic capacitance between wires due to the micro-wiring lead to lowering of the operation speed of the semiconductor devices, so that multilayer interconnection using a film with a low dielectric constant as an interlayer insulation film becomes necessary in accordance with the microminiaturization.
Reductions in the wiring widths and wiring pitches increase the aspect ratio of the space between wires as well as the aspect ratio of the wires themselves, and as a result, it imposes a great cost burden on the technology for forming micro wiring which are thin and long in the vertical direction and on the technology for embedding the space in the micro wiring with an interlayer insulation film, and increases the number of processes as well as makes the manufacturing process of the semiconductor device complicated.
Therefore, trench wiring technology (damascene technology) by which wiring trenches are formed in the interlayer insulation film and wiring materials are embedded in the wiring trenches by using the chemical-mechanical polishing (CMP) method attracts much attention. However, in the formation of wiring trenches or formation of via-holes, the formation of a CMP stopper film or an etching stopper film becomes necessary.
As such a stopper film, an insulation film is used, whose etching speed is different from that of the interlayer insulation film in which wiring trenches or via-holes are formed. Therefore, a technology for using an insulation film with a low dielectric constant as the interlayer insulation film and using a silicon nitride film (SiN film) or a silicon oxynitride film (SiON film) as the stopper film has been variously studied. Such a technology is disclosed in, for example, Japanese Patent Laid-open Publications No. Hei 10-116904 and No. Hei 10-229122.
A semiconductor device shall be described in which wiring is formed by the conventional dual damascene technology using a silicon nitride film or a silicon oxynitride film as a stopper film and using a Sixe2x80x94O-based coating film as an interlayer insulation film. FIG. 1 is a sectional view showing the conventional semiconductor device having the dual damascene wiring, and FIG. 2A through FIG. 2G are sectional views showing the manufacturing method for the semiconductor device in the order of the processes.
As shown in FIG. 1, protective insulation film 102 and first HSQ (hydrogen silsesquioxane) film 103 are successively formed on first wiring 101 formed from, for example, an aluminum-copper alloy. Etching stopper film 104 is deposited on this first HSQ film 103. This etching stopper film 104 is a SiN film or a SiON film deposited by the chemical vapor deposition (CVD) method.
Then, second HSQ film 105 is formed on the etching stopper film 104, and CMP stopper film 106 is further deposited on the second HSQ film 105. This CMP stopper film 106 is a SiN film or a SiON film deposited by the CVD method as the etching stopper film 104. Or, this CMP stopper film 106 may be a silicon oxide film deposited by the CVD method. Wiring trenches 108 and 108a are formed in a predetermined region of the second HSQ film 105 and CMP stopper film 106, and the protective insulation film 102 at the bottom of the etching stopper film 104, the first HSQ film 103, and the wiring trench 108 are opened to form via-hole 107 reaching the surface of the first wiring 101. Barrier layer 109 is formed on the inner wall of this via-hole 107 and wiring trenches 108, 108a, and second wirings 110 and 110a are formed to cover the barrier layer 109 and embed in the via-hole 107, wiring trench 108, and wiring trench 108a. 
Next, the method of manufacturing a conventional semiconductor device which has dual damascene wiring shall be described. As shown in FIG. 2A, a first wiring 101 formed from an aluminum-copper alloy is formed on a semiconductor substrate (not shown). A silicon oxide film with a thickness of approximately 50 nm is deposited on this first wiring 101 by the plasma CVD method to form protective insulation film 102. Then, a coating solution to become an HSQ film is applied on the entire surface, fired at approximately 200xc2x0 C., and further subjected to heat treatment at approximately 400xc2x0 C. in a diffusion furnace. The first HSQ film 103 with a thickness of 350 nm is thus formed.
Next, as shown in FIG. 2B, a silicon nitride film with a thickness of approximately 50 nm is deposited all over by the plasma CVD method. Etching stopper film 104 is thus formed on the first HSQ film 103.
Then, as shown in FIG. 2C, second HSQ film 105 is formed on the etching stopper film 104. The thickness of the second HSQ film 105 is approximately 500 nm, and the method of forming this film is the same as that for the abovementioned first HSQ film 103.
Next, as shown in FIG. 2D, a silicon oxide film with a thickness of approximately 50 nm is deposited on the entire surface by the plasma CVD method. CMP stopper film 106 is thus formed on the second HSQ film 105.
Next, as shown in FIG. 2E, first resist mask 111 is formed by the generally-known photolithography technique, and by using this first resist mask 111 as an etching mask, the CMP stopper film 106, the second HSQ film 105, the etching stopper film 104, and the first HSQ film 103 are dry-etched in order. Via-hole 107 to expose the surface of the protective insulation film 102 is thus formed.
Next, as shown in FIG. 2F, second resist mask 112 having a wiring trench pattern is formed, and by using the second resist mask 112 as an etching mask, the CMP stopper film 106 and the second HSQ film 105 are dry-etched in order. Thus wiring trenches 108, 108a are formed. At this time, a dry-etching gas and its material are selected so as to increase the etching selection ratio of the second HSQ film 105 and the etching stopper film 104, that is, so as to make the etching speed of the second HSQ film 105 higher than that of the etching stopper film 104.
The first HSQ film 103 is protected from being dry-etched by the etching stopper film 104 in the abovementioned etching process. In this process, the exposed protective insulation film 102 is simultaneously etched, and the via-hole 107 reaches the surface of the first wiring 101.
Next, as shown in FIG. 2G, the second resist mask 112 is removed. Then, a thin tantalum nitride (TaN) film is deposited on the entire surface by means of spattering to form barrier layer 109 on the inner walls of the via-hole 107 and the wiring trenches 108, 108a and on the surface of the CMP stopper film 106. Subsequently, a seed Cu film with a thickness of approximately 50 nm is deposited by means of spattering, and Cu film 113 with a thickness of approximately 1000 nm is further deposited by means of plating.
Next, not illustrated, the Cu film 113 and the barrier layer 109 are subjected to the CMP. In this CMP process, the second HSQ film 105 is protected from CMP by the CMP stopper film 106. The semiconductor device having the dual damascene wiring shown in FIG. 1 is thus formed.
However, in the prior-art mentioned above, the dielectric constant of the etching stopper film becomes high, and parasitic capacitance between the first wiring and the second wiring increases. In addition, as shown in FIG. 1, parasitic capacitance between the trench wiring 110 and the trench wiring 110a adjacent to each other increases due to the fringe effect between the same adjacent trenchs wiring via the etching stopper 104.
In the abovementioned example, the relative dielectric constant of the SiN film is 7 to 8, and the relative dielectric constant of the SiON film is approximately 5 to 6. This shows that these relative dielectric constants increases by two times or more the relative dielectric constant of the HSQ film which is approximately 3. Due to the increase in the parasitic capacitance between wirings, the operating speed of the semiconductor device, in particular, the operating speed of the logic-system semiconductor device lowers. Or, the formation of trench wiring by using a film with a low dielectric constant as the interlayer insulation film becomes impossible, and the lowering of the dielectric constant of the interlayer insulation film is limited. This is the first great problem.
A second problem is that a coating film with a low dielectric constant applied by an applying apparatus is used as a film with a low dielectric constant, and a film deposited by using a plasma CVD apparatus is used as an etching stopper film or a CMP stopper film, so that two manufacturing apparatuses becomes necessary, resulting in a huge capital investment cost.
A third problem is in that, when a Sixe2x80x94O based coating film having a methyl group such as the abovementioned MSQ (methyl silsesquioxane) film or MHSQ (methylated hydrogen silsesquioxane) film is used as the interlayer insulation film, adhesion between the MSQ film or MHSQ film and the silicon nitride film or silicon oxide film to be deposited on the MSQ or MHSQ film by the CVD method is poor, so that the CMP stopper film easily separates in the CMP process.
It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, wherein a Sixe2x80x94O based film with a low dielectric constant can be effectively used as an interlayer insulation film, the parasitic capacitance between the trench wirings can be reduced by a simple and easy method, and the number of manufacturing processes and the manufacturing cost of the semiconductor device are reduced.
A semiconductor device according to a first aspect of the present invention comprises: an interlayer insulation film having a reformed layer, formed at the surface of said interlayer insulation film, whose composition is changed from that of the inside of said interlayer insulation film; and a wiring formed on said reformed layer.
A semiconductor device according to a second aspect of the present invention comprises: a first interlayer insulation film having a reformed layer, formed at the surface of said first interlayer insulation film, whose composition is changed from that of the inside of said interlayer insulation film; a second interlayer insulation film formed on said reformed layer; a wiring trench formed in said second interlayer insulation film; and a wiring formed by embedding a conductive material in said wiring trench.
A semiconductor device according to a third aspect of the present invention comprises: a first interlayer insulation film having a first reformed layer, formed at the surface of said first interlayer insulation film, whose composition is changed from that of the inside of said first interlayer insulation film; a second interlayer insulation film having a second reformed layer, formed at the surface of said second interlayer insulation film, whose composition is changed from that of the inside of said second interlayer insulation film; a wiring trench formed in said second interlayer insulation film; and a wiring formed by embedding a conductive material in said wiring trench.
A semiconductor device according to a fourth aspect of the present invention comprises: a first interlayer insulation film having a first reformed layer, formed at the surface of said first interlayer insulation film, whose composition is changed from that of the inside of said first interlayer insulation film; a via-hole formed in said first interlayer insulation film; a via-hole formed by embedding a conductive material in said via-hole; a second interlayer insulation film having a reformed layer, formed at the surface of said second interlayer insulation film, whose composition is changed from that of the inside of said second interlayer insulation film; a wiring trench formed in said second interlayer insulation film; and a wiring formed by embedding the conductive material in said wiring trench.
Herein, the abovementioned interlayer insulation films including the first interlayer insulation film and the second interlayer insulation film are composed of silsesquioxanes or porous silica having one or more bonds selected from a group consisting of a Sixe2x80x94H bond, a Sixe2x80x94CH3 bond, and a Sixe2x80x94F bond, and the abovementioned reformed layers are composed of a silicon oxide film or a silicon dioxide film containing excess silicon. The above silsesquioxanes include hydrogen silsesquioxane, methyl silsesquioxane, methylated hydrogen silsesquioxane, and fluorinated silsesquioxane.
A method of manufacturing a semiconductor device according to a first aspect of the present invention comprises the steps of: forming an interlayer insulation film composed of silsesquioxanes or porous silica having one or more bonds selected from a group consisting of a Sixe2x80x94H bond, a Sixe2x80x94CH3 bond, and a Sixe2x80x94F bond; and forming a reformed layer made of a silicon oxide layer containing excess silicon or a silicon dioxide layer by irradiating a charged beam onto the surfaces of said interlayer insulation film to reform the surface of said interlayer insulation film.
A method of manufacturing a semiconductor device according to a second aspect of the present invention comprises the steps of: forming a first interlayer insulation film composed of silsesquioxanes or porous silica having one or more bonds selected from a group consisting of a Sixe2x80x94H bond, a Sixe2x80x94CH3 bond, and a Sixe2x80x94F bond; forming a reformed layer at the surface of said first interlayer insulation film by irradiating a charged beam onto the surface of said first interlayer insulation film; forming a second interlayer insulation film on said first reformed layer; forming a wiring trench in said second interlayer insulation film; and embedding a conductive film in said wiring trench.
A method of manufacturing a semiconductor device according to a third aspect of the present invention comprises the steps of: forming a first interlayer insulation film composed of silsesquioxanes or porous silica having one or more bonds selected from a group consisting of a Sixe2x80x94H bond, a Sixe2x80x94CH3 bond, and a Sixe2x80x94F bond; forming a first reformed layer at the surface of said first interlayer insulation film by irradiating a charged beam onto the surface of said first interlayer insulation film; forming a second interlayer insulation film on said first reformed layer compose of silsesquioxanes or porous silica having one or more bonds selected from a group consisting of a Sixe2x80x94H bond, a Sixe2x80x94CH3 bond, and a Sixe2x80x94F bond; forming a second reformed layer at the surface of said first interlayer insulation film by irradiating a charged beam onto the surface of said second interlayer insulation film; forming a wiring trench in said second reformed layer and said second interlayer insulation film; and embedding a conductive film in said wiring trench.
A method of manufacturing a semiconductor device according to a fourth aspect of the present invention comprises the steps of: forming a first interlayer insulation film composed of silsesquioxanes or porous silica having one or more bonds selected from a group consisting of a Sixe2x80x94H bond, a Sixe2x80x94CH3 bond, and a Sixe2x80x94F bond; forming a first reformed layer at the surface of said first interlayer insulation film by irradiating a charged beam onto the surface of said first interlayer insulation film; forming a second interlayer insulation film on said first interlayer insulation film, which is composed of silsesquioxanes or porous silica having one or more bonds selected from a group consisting of a Sixe2x80x94H bond, a Sixe2x80x94CH3 bond, and a Sixe2x80x94F bond; forming a second reformed layer at the surface of said second interlayer insulation film by irradiating a charged beam onto the surface of said second interlayer insulation film; forming a via-hole in said first reformed layer, said first interlayer insulation film, said second reformed layer, and said second interlayer insulation film; forming a wiring trench in said second reformed layer and said second interlayer insulation film; and embedding a conductive film in said via-hole and said wiring trench.
In the present invention, the first reformed layer is used as an etching stopper layer to protect the first interlayer insulation film, and the second interlayer insulation film is selectively dry-etched to form the wiring trenches. Furthermore, the second reformed layer is used as a chemical-mechanical polishing (CMP) stopper layer to protect the second interlayer insulation film, and the via-hole and the wiring trenches can be embedded with a conductive film through the chemical-mechanical polishing.
The silsesquioxanes include hydrogen silsesquioxane, methyl silsesquioxane, methylated hydrogen silsesquioxane, and fluorinated silsesquioxane, and the first reformed layer and the second reformed layer are composed of silicon oxide films or silicon dioxide films containing excess silicon. The charged beam is composed of an ionized rare gas or oxygen gas.
In the invention, a film with a low dielectric constant composed of a Sixe2x80x94O based coating film or the like is used as the interlayer insulation film between the wirings, and the surface of the interlayer insulation film is reformed by irradiation of a charged beam to form a reformed layer with a relatively low dielectric constant on the surface. In the formation of damascene wiring or dual damascene wiring, this reformed layer can be used as an etching stopper film or CMP stopper film as it is. This reformed layer has a structure, which gradually reforms at the interface from the interlayer insulation film, so that the adhesion between the reformed layer and the interlayer insulation film is extremely high. Therefore, the Sixe2x80x94O-based film with a low dielectric constant can be used for the interlayer insulation film, and parasitic capacitance between wiring can be easily reduced. Furthermore, the problem of separation of the stopper film in the CMP process as mentioned above in the prior-art is completely eliminated. Moreover, the formation of the reformed layers is easily performed by irradiation of charged beams, so that the manufacturing cost for the semiconductor device can be easily reduced. Thus, according to the invention, realization of high integration, high speed, and multifunction in accordance with microminiaturization of the semiconductor device can be promoted.